feat: make kernel architecture-agnostic; primitive work on arm port
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@@ -0,0 +1,246 @@
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;
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; S3Wake.asm
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; S3 suspend/resume: CPU state save and wake trampoline
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; Copyright (c) 2026 Daniel Hammer
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;
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[bits 64]
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section .text
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; ═════════════════════════════════════════════════════════════════════════════
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; AcpiSaveAndSuspend
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; ═════════════════════════════════════════════════════════════════════════════
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; extern "C" int AcpiSaveAndSuspend(CpuState* stateArea)
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; rdi = pointer to CpuState structure
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;
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; Saves all CPU registers into the CpuState structure, then returns 1.
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; The caller is expected to enter S3 after this returns.
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; On resume we rebuild the caller-visible stack frame and return to the
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; original Suspend() continuation via AcpiResumeEntry().
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;
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; Returns: 1 on initial call (proceed to enter S3)
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; Resume does not re-enter this function directly; control is
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; reconstructed by AcpiResumeLongMode/AcpiResumeEntry.
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;
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; CpuState layout:
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; 0x00 RAX 0x40 R8 0x80 RFLAGS
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; 0x08 RBX 0x48 R9 0x88 RIP
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; 0x10 RCX 0x50 R10 0x90 CR3
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; 0x18 RDX 0x58 R11 0x98 CR0
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; 0x20 RSI 0x60 R12 0xA0 CR4
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; 0x28 RDI 0x68 R13 0xA8 GDT (10 bytes)
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; 0x30 RBP 0x70 R14 0xB2 IDT (10 bytes)
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; 0x38 RSP 0x78 R15
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;
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global AcpiSaveAndSuspend
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AcpiSaveAndSuspend:
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; Save all general-purpose registers
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mov [rdi + 0x00], rax
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mov [rdi + 0x08], rbx
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mov [rdi + 0x10], rcx
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mov [rdi + 0x18], rdx
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mov [rdi + 0x20], rsi
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mov [rdi + 0x28], rdi ; save rdi (pointer to state area)
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mov [rdi + 0x30], rbp
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; Save the caller's post-return RSP, not our own entry RSP. The raw
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; entry RSP points at this call's temporary return-address slot, which
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; the suspend path will later reuse for other calls before the machine
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; actually enters S3.
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lea rax, [rsp + 8]
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mov [rdi + 0x38], rax
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mov [rdi + 0x40], r8
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mov [rdi + 0x48], r9
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mov [rdi + 0x50], r10
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mov [rdi + 0x58], r11
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mov [rdi + 0x60], r12
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mov [rdi + 0x68], r13
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mov [rdi + 0x70], r14
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mov [rdi + 0x78], r15
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; Save RFLAGS
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pushfq
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pop rax
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mov [rdi + 0x80], rax
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; Save return address as resume RIP
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mov rax, [rsp] ; return address on stack
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mov [rdi + 0x88], rax
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; Save control registers
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mov rax, cr3
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mov [rdi + 0x90], rax
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mov rax, cr0
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mov [rdi + 0x98], rax
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mov rax, cr4
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mov [rdi + 0xA0], rax
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; Save GDT pointer (offset 0xA8)
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sgdt [rdi + 0xA8]
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; Save IDT pointer (offset 0xB2)
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sidt [rdi + 0xB2]
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; Return 1 = "initial save, now enter S3"
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mov rax, 1
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ret
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; ═════════════════════════════════════════════════════════════════════════════
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; AcpiWakeEntry
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; ═════════════════════════════════════════════════════════════════════════════
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; This is the actual waking vector target. Firmware jumps here after S3
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; resume. It loads the CpuState pointer from a fixed location (set before
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; suspend) and falls through to AcpiResumeLongMode.
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;
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; For 64-bit waking vector (X_FirmwareWakingVector): firmware resumes in
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; long mode and jumps directly here. We load rdi from the saved pointer
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; and proceed to restore state.
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;
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; For QEMU with OVMF and similar UEFI firmware, the 64-bit path works.
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; Real-mode (32-bit FirmwareWakingVector) wake is not yet supported.
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;
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global AcpiWakeEntry
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AcpiWakeEntry:
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; Clear direction flag (firmware may have left it set)
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cld
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; Load the CpuState pointer from the well-known location.
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; g_wakeStatePtr is set by the C code before entering S3.
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lea rdi, [rel g_wakeStatePtr]
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mov rdi, [rdi]
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; Fall through to restore all state
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jmp AcpiResumeLongMode
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; ═════════════════════════════════════════════════════════════════════════════
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; Well-known pointer to CpuState (set before suspend)
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; ═════════════════════════════════════════════════════════════════════════════
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; Placed in .text so AcpiWakeEntry can use RIP-relative addressing
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; without a cross-section relocation warning.
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; extern "C" void* g_wakeStatePtr;
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global g_wakeStatePtr
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g_wakeStatePtr: dq 0
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; ═════════════════════════════════════════════════════════════════════════════
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; AcpiResumeLongMode
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; ═════════════════════════════════════════════════════════════════════════════
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; extern "C" void AcpiResumeLongMode(CpuState* stateArea)
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; rdi = pointer to CpuState structure
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;
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; Restores the saved machine state, reconstructs the original Suspend()
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; continuation on the stack, and then jumps into the C resume path.
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;
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global AcpiResumeLongMode
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AcpiResumeLongMode:
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; Progress: reached AcpiResumeLongMode (0xC1)
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mov al, 0xF2
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out 0x70, al
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mov al, 0xC1
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out 0x71, al
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; At entry: rdi = CpuState*, RSP = trampoline stack (unmapped junk),
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; CR3 = kernel PML4 (loaded by trampoline), CS = trampoline selector.
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;
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; We must restore the kernel stack FIRST so push/pop work, then reload
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; GDT/CS/IDT before any interrupt can fire.
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; Restore the caller-visible kernel RSP immediately so we have a valid
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; stack. AcpiSaveAndSuspend saved the post-return value (RSP after the
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; original call had completed), so we will reconstruct the return address
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; explicitly below before entering C.
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mov rsp, [rdi + 0x38]
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; Restore GDT
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lgdt [rdi + 0xA8]
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; Reload CS to kernel code selector (0x08) via far return.
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; Without this, CS still holds the trampoline's selector (0x18)
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; which maps to UserData in the kernel GDT → #GP on first interrupt.
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push 0x08 ; kernel code selector
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lea rax, [rel .reload_cs]
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push rax
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retfq
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.reload_cs:
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; Progress: GDT + CS reloaded (0xC2)
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mov al, 0xF2
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out 0x70, al
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mov al, 0xC2
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out 0x71, al
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; Reload data segment registers with kernel data selector
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mov ax, 0x10
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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; Restore IDT
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lidt [rdi + 0xB2]
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; Restore CR4 before CR3 — PGE, PAE, OSFXSR etc. must be set before
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; the page table switch. The trampoline only set minimal bits (PAE).
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; Real hardware needs the full saved CR4 (especially PGE for TLB
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; correctness and WP in CR0 for write-protect enforcement).
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mov rax, [rdi + 0xA0]
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mov cr4, rax
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; Restore CR0 (WP, NE, etc.)
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mov rax, [rdi + 0x98]
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mov cr0, rax
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; Restore saved CR3 (process PML4). The trampoline used the kernel
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; master PML4 to get here; now switch to the actual saved context.
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mov rax, [rdi + 0x90]
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mov cr3, rax
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; Progress: IDT + CR4/CR0/CR3 restored (0xC3)
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mov al, 0xF2
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out 0x70, al
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mov al, 0xC3
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out 0x71, al
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; Restore general-purpose registers (skip RSP — already restored above)
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mov rbx, [rdi + 0x08]
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mov rcx, [rdi + 0x10]
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mov rdx, [rdi + 0x18]
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mov rsi, [rdi + 0x20]
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mov rbp, [rdi + 0x30]
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mov r8, [rdi + 0x40]
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mov r9, [rdi + 0x48]
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mov r10, [rdi + 0x50]
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mov r11, [rdi + 0x58]
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mov r12, [rdi + 0x60]
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mov r13, [rdi + 0x68]
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mov r14, [rdi + 0x70]
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mov r15, [rdi + 0x78]
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; Restore RFLAGS but keep IF masked until AcpiResumeEntry finishes
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; rebuilding GS base, TSS, APIC, and the rest of the interrupt state.
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; The saved flags usually have IF=1 because Suspend() is entered from a
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; live syscall path; restoring that too early lets an IRQ hit a
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; half-restored kernel.
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mov rax, [rdi + 0x80]
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and rax, ~(1 << 9)
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push rax
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popfq
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; Progress: about to call AcpiResumeEntry (0xC4)
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mov al, 0xF2
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out 0x70, al
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mov al, 0xC4
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out 0x71, al
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; Reconstruct the original return address. The suspend path ran many more
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; calls after AcpiSaveAndSuspend returned, so the old call-frame slot on
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; the kernel stack can no longer be trusted.
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push qword [rdi + 0x88]
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; Instead of re-entering Suspend() directly from assembly, jump to a
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; dedicated C resume function which rebuilds the rest of the runtime
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; environment and then returns to the original caller via the RIP we just
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; pushed.
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extern AcpiResumeEntry
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jmp AcpiResumeEntry
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