feat: make kernel architecture-agnostic; primitive work on arm port
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@@ -0,0 +1,201 @@
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;
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; IsrStubs.asm
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; Hardware interrupt (IRQ) entry stubs for APIC (SMP-aware with SWAPGS)
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; Copyright (c) 2025-2026 Daniel Hammer
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;
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[bits 64]
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section .text
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; External C++ handler function
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extern HalIrqDispatch
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; ====================================================================
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; IRQ stub macro with SWAPGS support
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; Each stub checks the saved CS to determine if we came from user mode.
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; If so, SWAPGS is executed to switch GS to per-CPU data.
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; ====================================================================
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%macro IRQ_STUB 1
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global IrqStub%1
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IrqStub%1:
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cmp qword [rsp + 8], 0x08 ; check saved CS: kernel?
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je %%from_kernel
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swapgs ; from user mode: swap to kernel GS
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%%from_kernel:
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push rax ; save rax (used for IRQ number)
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mov rax, %1 ; IRQ number
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jmp IrqCommon
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%endmacro
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; ====================================================================
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; Common IRQ handler: saves all general-purpose registers,
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; calls the C++ dispatch function, restores registers, and returns.
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; ====================================================================
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IrqCommon:
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; rax is already on the stack and holds the IRQ number
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push rcx
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push rdx
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push rbx
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push rbp
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push rsi
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push rdi
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push r8
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push r9
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push r10
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push r11
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push r12
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push r13
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push r14
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push r15
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; Pass IRQ number as first argument (rdi)
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mov rdi, rax
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; Pass the saved CS as the second argument. Fifteen saved GPRs occupy
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; 120 bytes, and CS is eight bytes after the interrupt-frame RIP.
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mov rsi, [rsp + 128]
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; An IRQ that interrupted ring 0 can arrive at any kernel stack depth, so
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; the saved frame is not guaranteed to satisfy the SysV call alignment.
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; RBX is already saved above and is callee-saved, making it a safe place to
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; retain the exact frame pointer while aligning down for the C++ call.
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mov rbx, rsp
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and rsp, -16
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cld
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call HalIrqDispatch
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mov rsp, rbx
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pop r15
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pop r14
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pop r13
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pop r12
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pop r11
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pop r10
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pop r9
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pop r8
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pop rdi
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pop rsi
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pop rbp
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pop rbx
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pop rdx
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pop rcx
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pop rax
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; SWAPGS back if returning to user mode
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cmp qword [rsp + 8], 0x08 ; check saved CS: kernel?
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je .from_kernel_exit
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swapgs ; returning to user mode: restore user GS
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.from_kernel_exit:
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iretq
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; ====================================================================
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; Define stubs for IRQs 0..47 (vectors 32..79)
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; 0-23: legacy ISA IRQs via IOAPIC, 24-45: MSI, 46-47: kernel IPIs
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; ====================================================================
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IRQ_STUB 0
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IRQ_STUB 1
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IRQ_STUB 2
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IRQ_STUB 3
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IRQ_STUB 4
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IRQ_STUB 5
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IRQ_STUB 6
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IRQ_STUB 7
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IRQ_STUB 8
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IRQ_STUB 9
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IRQ_STUB 10
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IRQ_STUB 11
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IRQ_STUB 12
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IRQ_STUB 13
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IRQ_STUB 14
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IRQ_STUB 15
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IRQ_STUB 16
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IRQ_STUB 17
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IRQ_STUB 18
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IRQ_STUB 19
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IRQ_STUB 20
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IRQ_STUB 21
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IRQ_STUB 22
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IRQ_STUB 23
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IRQ_STUB 24
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IRQ_STUB 25
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IRQ_STUB 26
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IRQ_STUB 27
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IRQ_STUB 28
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IRQ_STUB 29
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IRQ_STUB 30
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IRQ_STUB 31
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IRQ_STUB 32
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IRQ_STUB 33
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IRQ_STUB 34
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IRQ_STUB 35
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IRQ_STUB 36
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IRQ_STUB 37
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IRQ_STUB 38
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IRQ_STUB 39
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IRQ_STUB 40
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IRQ_STUB 41
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IRQ_STUB 42
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IRQ_STUB 43
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IRQ_STUB 44
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IRQ_STUB 45
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IRQ_STUB 46
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IRQ_STUB 47
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; Spurious interrupt handler (vector 0xFF) - do nothing, no EOI
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global IrqStubSpurious
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IrqStubSpurious:
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iretq
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; ====================================================================
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; Export the stub table for C++ to reference
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; ====================================================================
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section .data
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global IrqStubTable
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IrqStubTable:
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dq IrqStub0
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dq IrqStub1
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dq IrqStub2
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dq IrqStub3
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dq IrqStub4
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dq IrqStub5
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dq IrqStub6
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dq IrqStub7
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dq IrqStub8
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dq IrqStub9
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dq IrqStub10
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dq IrqStub11
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dq IrqStub12
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dq IrqStub13
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dq IrqStub14
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dq IrqStub15
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dq IrqStub16
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dq IrqStub17
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dq IrqStub18
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dq IrqStub19
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dq IrqStub20
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dq IrqStub21
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dq IrqStub22
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dq IrqStub23
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dq IrqStub24
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dq IrqStub25
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dq IrqStub26
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dq IrqStub27
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dq IrqStub28
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dq IrqStub29
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dq IrqStub30
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dq IrqStub31
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dq IrqStub32
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dq IrqStub33
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dq IrqStub34
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dq IrqStub35
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dq IrqStub36
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dq IrqStub37
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dq IrqStub38
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dq IrqStub39
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dq IrqStub40
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dq IrqStub41
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dq IrqStub42
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dq IrqStub43
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dq IrqStub44
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dq IrqStub45
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dq IrqStub46
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dq IrqStub47
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