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feat: graphics/net PnP, keyboard driver improvements

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daniel
2026-03-04 21:10:34 +01:00
parent 704b80ca4b
commit 5dded4bda0
18 changed files with 836 additions and 244 deletions
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kernel/src/Drivers/Graphics/IntelGPU.cpp
+91 -12
View File
@@ -132,14 +132,7 @@ namespace Drivers::Graphics::IntelGPU {
uint8_t func = g_gpuInfo.pciFunction;
// Read BAR0
uint32_t bar0Low = Pci::LegacyRead32(bus, dev, func, (uint8_t)PCI_REG_BAR0);
uint64_t mmioPhys = bar0Low & 0xFFFFFFF0u; // Mask off type/prefetchable bits
// Check for 64-bit BAR (bit 2 of BAR type field)
if (bar0Low & 0x04) {
uint32_t bar0High = Pci::LegacyRead32(bus, dev, func, (uint8_t)(PCI_REG_BAR0 + 4));
mmioPhys |= ((uint64_t)bar0High << 32);
}
uint64_t mmioPhys = Pci::ReadBar0(bus, dev, func);
g_gpuInfo.mmioPhys = mmioPhys;
g_gpuInfo.mmioSize = 0x200000; // Map 2MB of MMIO space
@@ -155,10 +148,8 @@ namespace Drivers::Graphics::IntelGPU {
KernelLogStream(OK, "IntelGPU") << "MMIO mapped at virtual " << base::hex << (uint64_t)g_mmioBase;
// Enable memory space and bus master in PCI command register
uint16_t pciCmd = Pci::LegacyRead16(bus, dev, func, (uint8_t)PCI_REG_COMMAND);
pciCmd |= PCI_CMD_MEM_SPACE | PCI_CMD_BUS_MASTER;
Pci::LegacyWrite16(bus, dev, func, (uint8_t)PCI_REG_COMMAND, pciCmd);
// Enable memory space and bus master
Pci::EnableBusMaster(bus, dev, func);
KernelLogStream(OK, "IntelGPU") << "PCI memory space and bus mastering enabled";
@@ -473,6 +464,94 @@ namespace Drivers::Graphics::IntelGPU {
// Public API
// =========================================================================
// =========================================================================
// Probe (called by PCI driver matching framework)
// =========================================================================
bool Probe(const Pci::PciDevice& dev) {
if (g_initialized) return false;
// Fill in PCI location
g_gpuInfo.pciBus = dev.Bus;
g_gpuInfo.pciDevice = dev.Device;
g_gpuInfo.pciFunction = dev.Function;
g_gpuInfo.deviceId = dev.DeviceId;
// Match device ID against supported table
const DeviceInfo* matchedInfo = nullptr;
for (int j = 0; j < SupportedDeviceCount; j++) {
if (dev.DeviceId == SupportedDevices[j].deviceId) {
matchedInfo = &SupportedDevices[j];
break;
}
}
if (matchedInfo != nullptr) {
g_gpuInfo.gen = matchedInfo->gen;
g_gpuInfo.name = matchedInfo->name;
KernelLogStream(OK, "IntelGPU") << "Found " << matchedInfo->name
<< " (device " << base::hex << (uint64_t)dev.DeviceId << ")"
<< " at PCI " << (uint64_t)dev.Bus << ":"
<< (uint64_t)dev.Device << "." << (uint64_t)dev.Function;
} else {
g_gpuInfo.gen = 7;
g_gpuInfo.name = "Intel GPU";
KernelLogStream(WARNING, "IntelGPU") << "Unknown Intel display controller "
<< "(device " << base::hex << (uint64_t)dev.DeviceId << ")"
<< " at PCI " << (uint64_t)dev.Bus << ":"
<< (uint64_t)dev.Device << "." << (uint64_t)dev.Function
<< " - attempting generic initialization";
}
g_gpuGen = g_gpuInfo.gen;
if (!MapMmio()) {
KernelLogStream(ERROR, "IntelGPU") << "Failed to map MMIO region";
return false;
}
DisableVga();
if (!ReadDisplayState()) {
KernelLogStream(ERROR, "IntelGPU") << "Failed to read display state";
return false;
}
if (!InitializeGtt()) {
KernelLogStream(ERROR, "IntelGPU") << "Failed to initialize GTT";
return false;
}
if (!SetupFramebuffer()) {
KernelLogStream(ERROR, "IntelGPU") << "Failed to set up framebuffer";
return false;
}
ProgramDisplayPlane();
g_initialized = true;
uint64_t fwWidth = ::Graphics::Cursor::GetFramebufferWidth();
uint64_t fwHeight = ::Graphics::Cursor::GetFramebufferHeight();
uint64_t fwPitch = ::Graphics::Cursor::GetFramebufferPitch();
if (g_fbWidth != fwWidth || g_fbHeight != fwHeight || g_fbPitch != fwPitch) {
KernelLogStream(WARNING, "IntelGPU") << "GPU dimensions differ from firmware!";
KernelLogStream(WARNING, "IntelGPU") << " GPU: "
<< base::dec << g_fbWidth << "x" << g_fbHeight << " pitch=" << g_fbPitch;
KernelLogStream(WARNING, "IntelGPU") << " Firmware: "
<< base::dec << fwWidth << "x" << fwHeight << " pitch=" << fwPitch;
}
KernelLogStream(OK, "IntelGPU") << "Initialization complete: "
<< base::dec << g_fbWidth << "x" << g_fbHeight
<< " @ " << base::hex << (uint64_t)g_fbBase;
return true;
}
// =========================================================================
// Initialize (standalone fallback path)
// =========================================================================
void Initialize() {
KernelLogStream(INFO, "IntelGPU") << "Scanning for Intel integrated graphics...";
kernel/src/Drivers/Graphics/IntelGPU.hpp
+5 -7
View File
@@ -7,6 +7,7 @@
#pragma once
#include <cstdint>
#include <Pci/Pci.hpp>
namespace Drivers::Graphics::IntelGPU {
@@ -18,14 +19,8 @@ namespace Drivers::Graphics::IntelGPU {
static constexpr uint8_t ClassDisplay = 0x03;
static constexpr uint8_t SubclassVGA = 0x00;
// PCI config space offsets
static constexpr uint16_t PCI_REG_BAR0 = 0x10;
// PCI config space offsets (GPU-specific, not in shared Pci::)
static constexpr uint16_t PCI_REG_BAR2 = 0x18;
static constexpr uint16_t PCI_REG_COMMAND = 0x04;
static constexpr uint16_t PCI_CMD_MEM_SPACE = (1 << 1);
static constexpr uint16_t PCI_CMD_BUS_MASTER = (1 << 2);
// Graphics control register (PCI config offset 0x50 on SNB+)
static constexpr uint16_t PCI_REG_GMCH_CTL = 0x50;
// Supported Intel GPU device IDs (representative subset)
@@ -400,6 +395,9 @@ namespace Drivers::Graphics::IntelGPU {
// Initialize the Intel GPU driver (scans PCI, maps MMIO, sets up GTT + FB)
void Initialize();
// Probe a specific PCI device (called by PCI driver matching framework)
bool Probe(const Pci::PciDevice& dev);
// Check if an Intel GPU was found and initialized
bool IsInitialized();