feat: aarch64 port - fix build system obstacles, add exception handling, page tables

kernel/src/Arch/aarch64/Cpu.hpp

@@ -92,9 +92,10 @@ namespace Arch {
         asm volatile("dsb sy\n\tisb" ::: "memory");
     }
 
+    // The TLBI operand is VA[55:12] in bits [43:0]; the bits above are RES0.
     inline void FlushTlbPage(uint64_t virtualAddress) {
         asm volatile("dsb ishst\n\ttlbi vaae1is, %0\n\tdsb ish\n\tisb"
-                     :: "r"(virtualAddress >> 12) : "memory");
+                     :: "r"((virtualAddress >> 12) & ((1ULL << 44) - 1)) : "memory");
     }
 
     inline void FlushTlbAll() {