feat: aarch64 port - fix build system obstacles, add exception handling, page tables
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/*
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* Uart.cpp
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* Polled serial console from the ACPI SPCR table
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* Copyright (c) 2026 Daniel Hammer
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*/
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#include "Uart.hpp"
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#include <Terminal/Terminal.hpp>
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#include <CppLib/Stream.hpp>
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#include <Memory/HHDM.hpp>
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#include <Memory/Paging.hpp>
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#include <Io/IoPort.hpp>
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#include <Arch/Cpu.hpp>
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using namespace Kt;
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namespace Drivers::Serial {
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struct GenericAddress {
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uint8_t AddressSpaceId; // 0 = system memory, 1 = system I/O
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uint8_t RegisterBitWidth;
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uint8_t RegisterBitOffset;
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uint8_t AccessSize; // 1 = byte, 2 = word, 3 = dword, 4 = qword
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uint64_t Address;
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} __attribute__((packed));
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struct Spcr {
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Hal::ACPI::CommonSDTHeader Header;
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uint8_t InterfaceType;
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uint8_t Reserved[3];
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GenericAddress BaseAddress;
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uint8_t InterruptType;
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uint8_t Irq;
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uint32_t GlobalSystemInterrupt;
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uint8_t BaudRate;
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uint8_t Parity;
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uint8_t StopBits;
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uint8_t FlowControl;
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uint8_t TerminalType;
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} __attribute__((packed));
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// SPCR / DBG2 serial interface subtypes
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static constexpr uint8_t Type16550 = 0x00;
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static constexpr uint8_t Type16450 = 0x01;
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static constexpr uint8_t TypePl011 = 0x03;
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static constexpr uint8_t TypeSbsa32 = 0x0D;
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static constexpr uint8_t TypeSbsaGeneric = 0x0E;
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static constexpr uint8_t TypeBcm2835 = 0x10;
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static constexpr uint8_t Type16550Generic = 0x12;
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// PL011: data register, flag register (TX FIFO full)
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static constexpr uint64_t Pl011Dr = 0x00;
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static constexpr uint64_t Pl011Fr = 0x18;
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static constexpr uint32_t Pl011FrTxff = 1u << 5;
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// 16550: transmit holding register, line status register (THR empty)
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static constexpr uint64_t Uart16550Thr = 0;
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static constexpr uint64_t Uart16550Lsr = 5;
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static constexpr uint8_t Uart16550LsrThre = 1u << 5;
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// Bounded so a wedged or absent UART cannot hang the console.
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static constexpr int TxSpinLimit = 100000;
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static volatile uint8_t* g_mmio = nullptr;
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static uint16_t g_port = 0;
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static uint32_t g_stride = 1;
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static inline uint32_t Read32(uint64_t offset) {
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return *(volatile uint32_t*)(g_mmio + offset);
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}
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static inline void Write32(uint64_t offset, uint32_t value) {
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*(volatile uint32_t*)(g_mmio + offset) = value;
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}
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static void Pl011Putchar(char c) {
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for (int i = 0; i < TxSpinLimit && (Read32(Pl011Fr) & Pl011FrTxff); i++) {
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Arch::Pause();
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}
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Write32(Pl011Dr, (uint8_t)c);
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}
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static uint8_t Mmio16550Read(uint64_t reg) {
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if (g_stride == 4) return (uint8_t)Read32(reg * 4);
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return g_mmio[reg];
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}
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static void Mmio16550Write(uint64_t reg, uint8_t value) {
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if (g_stride == 4) Write32(reg * 4, value);
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else g_mmio[reg] = value;
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}
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static void Mmio16550Putchar(char c) {
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for (int i = 0; i < TxSpinLimit && !(Mmio16550Read(Uart16550Lsr) & Uart16550LsrThre); i++) {
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Arch::Pause();
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}
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Mmio16550Write(Uart16550Thr, (uint8_t)c);
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}
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static void Port16550Putchar(char c) {
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for (int i = 0; i < TxSpinLimit && !(Io::In8(g_port + Uart16550Lsr) & Uart16550LsrThre); i++) {
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Arch::Pause();
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}
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Io::Out8((uint8_t)c, g_port + Uart16550Thr);
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}
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static Spcr* FindSpcr(Hal::ACPI::CommonSDTHeader* xsdt) {
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uint32_t entryCount = (xsdt->Length - sizeof(Hal::ACPI::CommonSDTHeader)) / 8;
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uint64_t* entries = (uint64_t*)((uint64_t)xsdt + sizeof(Hal::ACPI::CommonSDTHeader));
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for (uint32_t i = 0; i < entryCount; i++) {
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auto* header = (Hal::ACPI::CommonSDTHeader*)Memory::HHDM(entries[i]);
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const char* sig = header->Signature;
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if (sig[0] == 'S' && sig[1] == 'P' && sig[2] == 'C' && sig[3] == 'R') {
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return (Spcr*)header;
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}
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}
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return nullptr;
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}
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static volatile uint8_t* MapRegisters(uint64_t phys) {
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uint64_t page = phys & ~0xFFFULL;
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Memory::VMM::g_paging->MapMMIO(page, Memory::HHDM(page));
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return (volatile uint8_t*)Memory::HHDM(phys);
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}
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void InitializeConsole(Hal::ACPI::CommonSDTHeader* xsdt) {
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if (xsdt == nullptr) return;
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Spcr* spcr = FindSpcr(xsdt);
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if (spcr == nullptr || spcr->Header.Length < sizeof(Spcr)) {
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return;
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}
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const GenericAddress& reg = spcr->BaseAddress;
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if (reg.Address == 0) return;
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SerialSink sink = nullptr;
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const char* name = "";
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bool isIo = reg.AddressSpaceId == 1;
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switch (spcr->InterfaceType) {
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case TypePl011:
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case TypeSbsa32:
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case TypeSbsaGeneric:
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if (isIo) return;
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g_mmio = MapRegisters(reg.Address);
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sink = Pl011Putchar;
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name = "PL011";
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break;
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case Type16550:
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case Type16450:
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case Type16550Generic:
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case TypeBcm2835:
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if (isIo) {
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if (!Io::HasPortIo) return;
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g_port = (uint16_t)reg.Address;
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sink = Port16550Putchar;
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} else {
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// The BCM2835 mini UART is a 16550 with 32-bit registers.
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g_stride = (reg.RegisterBitWidth == 32 || reg.AccessSize == 3
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|| spcr->InterfaceType == TypeBcm2835) ? 4 : 1;
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g_mmio = MapRegisters(reg.Address);
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sink = Mmio16550Putchar;
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}
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name = spcr->InterfaceType == TypeBcm2835 ? "BCM2835 mini UART" : "16550";
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break;
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default:
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KernelLogStream(WARNING, "Serial") << "SPCR interface type 0x" << base::hex
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<< (uint64_t)spcr->InterfaceType << " not supported";
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return;
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}
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AttachSerialConsole(sink);
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KernelLogStream(OK, "Serial") << "Console on " << name << " at " << (isIo ? "port " : "")
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<< "0x" << base::hex << reg.Address;
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}
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}
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@@ -0,0 +1,18 @@
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/*
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* Uart.hpp
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* Polled serial console from the ACPI SPCR table
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* Copyright (c) 2026 Daniel Hammer
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*/
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#pragma once
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#include <ACPI/ACPI.hpp>
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namespace Drivers::Serial {
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// Find the firmware's serial console (SPCR: PL011, SBSA generic UART,
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// 16550 or the BCM2835 mini UART) and mirror the kernel console to it.
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// Uses the baud rate the firmware configured. Needs the kernel page
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// tables (the registers are mapped uncached through the HHDM).
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void InitializeConsole(Hal::ACPI::CommonSDTHeader* xsdt);
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}
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