feat: aarch64 port - fix build system obstacles, add exception handling, page tables
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@@ -187,7 +187,20 @@ namespace Pci {
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Io::Out32(value, ConfigDataPort);
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}
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// Drivers reach config space through the Legacy* calls below. Without
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// an I/O address space (ARM) there is no CF8/CFC mechanism, so they use
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// ECAM there, at the access's own width (16/8-bit writes must not
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// read-modify-write a neighbouring RW1C register).
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static bool EcamCovers(uint8_t bus);
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static bool UseEcamForLegacy(uint8_t bus) {
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return !Io::HasPortIo && EcamCovers(bus);
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}
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uint32_t LegacyRead32(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset) {
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if (UseEcamForLegacy(bus)) {
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return EcamRead32(g_ecamBase, bus, device, function, offset & 0xFC);
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}
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g_legacyConfigLock.Acquire();
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uint32_t value = LegacyRead32Unlocked(bus, device, function, offset);
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g_legacyConfigLock.Release();
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@@ -205,12 +218,20 @@ namespace Pci {
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}
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void LegacyWrite32(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset, uint32_t value) {
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if (UseEcamForLegacy(bus)) {
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EcamWrite32(g_ecamBase, bus, device, function, offset & 0xFC, value);
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return;
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}
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g_legacyConfigLock.Acquire();
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LegacyWrite32Unlocked(bus, device, function, offset, value);
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g_legacyConfigLock.Release();
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}
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void LegacyWrite16(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset, uint16_t value) {
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if (UseEcamForLegacy(bus)) {
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EcamWrite16(g_ecamBase, bus, device, function, offset & 0xFE, value);
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return;
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}
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g_legacyConfigLock.Acquire();
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uint32_t tmp = LegacyRead32Unlocked(bus, device, function, offset & 0xFC);
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int shift = (offset & 2) * 8;
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@@ -221,6 +242,10 @@ namespace Pci {
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}
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void LegacyWrite8(uint8_t bus, uint8_t device, uint8_t function, uint8_t offset, uint8_t value) {
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if (UseEcamForLegacy(bus)) {
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EcamWrite8(g_ecamBase, bus, device, function, offset, value);
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return;
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}
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g_legacyConfigLock.Acquire();
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uint32_t tmp = LegacyRead32Unlocked(bus, device, function, offset & 0xFC);
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int shift = (offset & 3) * 8;
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