feat: add support for aarch64 timer/interrupts, port MontaukOS userspace

kernel/src/Arch/aarch64/Cpu.hpp

@@ -93,6 +93,21 @@ namespace Arch {
     }
 
     // The TLBI operand is VA[55:12] in bits [43:0]; the bits above are RES0.
+    // Clean the data cache to the point of unification, then invalidate
+    // the whole instruction cache: invalidating by address would only
+    // reach the alias it names on an aliasing (VIPT) instruction cache.
+    inline void SyncInstructionCache(const void* address, uint64_t size) {
+        uint64_t ctr;
+        asm volatile("mrs %0, ctr_el0" : "=r"(ctr));
+        uint64_t line = 4ULL << ((ctr >> 16) & 0xF);  // DminLine
+        uint64_t start = (uint64_t)address & ~(line - 1);
+        uint64_t end = (uint64_t)address + size;
+        for (uint64_t p = start; p < end; p += line) {
+            asm volatile("dc cvau, %0" :: "r"(p) : "memory");
+        }
+        asm volatile("dsb ish\n\tic ialluis\n\tdsb ish\n\tisb" ::: "memory");
+    }
+
     inline void FlushTlbPage(uint64_t virtualAddress) {
         asm volatile("dsb ishst\n\ttlbi vaae1is, %0\n\tdsb ish\n\tisb"
                      :: "r"((virtualAddress >> 12) & ((1ULL << 44) - 1)) : "memory");